Draft BS EN 62228-5 Integrated circuits. EMC evaluation of transceivers Part 5. Ethernet
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Parameter extraction techniques for the European mini test chip
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Measurement techniques for the characterization of the European mini test chip
Description of a parametrized European mini test chip
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Description of the reliability test structures of the European mini test chip
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JESSI 0.8 µm CMOS transistor model for analogue and digital circuit simulation
Harmonized system of quality assessment for electronic components. Semiconductor devices Generic specification
Harmonized system of quality assessment for electronic components: generic specification: film and hybrid integrated circuits
Harmonized system of quality assessment for electronic components: sectional specification: digital monolithic integrated circuits
Specification for harmonized system of quality assessment for electronic components. Blank detail specification: fusible link programmable read only memories, silicon monolithic integrated circuits
Specification for harmonized system of quality assessment for electronic components. Family specification: advanced low power TTL SCHOTTKY integrated circuits
Specification for harmonized system of quality assessment for electronic components. Family specification: digital integrated TTL FAST circuits
Harmonized system of quality assessment for electronic components. Sectional specification: analogue monolithic integrated circuits
Harmonized system of quality assessment for electronic components. Sectional specification: interface monolithic integrated circuits
Specification for harmonized system of quality assessment for electronic components. Blank detail specification: digital microprocessor integrated circuits
