Superseded
Standard
Historical
IEC 62530:2007
Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
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Summary
Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>
Technical characteristics
| Publisher | International Electrotechnical Commission (IEC) |
| Publication Date | 11/07/2007 |
| Release Date | 11/07/2007 |
| Cancellation Date | 05/19/2011 |
| Edition | 1 |
| Page Count | 663 |
| EAN | --- |
| ISBN | --- |
| Weight (in grams) | --- |
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Previous versions
07/11/2007
Superseded
Historical
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