Withdrawn
Standard
Most Recent
IEC 62142:2005
Verilog (R) register transfer level synthesis
Preview
Summary
Defines a set of modeling rules for writing Verilog®
HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL
are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL
are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
Technical characteristics
| Publisher | International Electrotechnical Commission (IEC) |
| Publication Date | 06/27/2005 |
| Release Date | 06/27/2005 |
| Cancellation Date | 08/04/2010 |
| Edition | 1 |
| Page Count | 109 |
| EAN | --- |
| ISBN | --- |
| Weight (in grams) | --- |
No products.
Previous versions
No products.