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IEC 62050:2005

VHDL Register Transfer Level (RTL) synthesis

Summary

Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

Technical characteristics

Publisher International Electrotechnical Commission (IEC)
Publication Date 07/19/2005
Release Date 07/19/2005
Cancellation Date 08/04/2010
Edition 1
Page Count 121
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