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ISO/IEC 18372:2004
ISO/IEC 18372:2004 Information technology - RapidIO TM interconnect specification
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Summary
The electronic version of this International Standard can be downloadedfrom the ISO/IEC Information Technology Task Force (ITTF) web site.
The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.
The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.
Technical characteristics
| Publisher | International Organization for Standardization (ISO) / International Electrotechnical Commission (IEC) |
| Publication Date | 12/15/2004 |
| Edition | 1.0 |
| Page Count | 399 |
| EAN | --- |
| ISBN | --- |
| Weight (in grams) | --- |
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