| Nombre | apoyo | Revisión | Disponibilidad | Fecha de emisión | Precio | ||
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PDF sécurisé |
Inglés |
Vigente |
1/9/2018 |
385,25 € |
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Detalles
This Standard was technically approved by the Silicon Wafer Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on August 17, 2018, available at www.semiviews.org and www.semi.org in September 2018. Originally published in 1978, previously published November 2017.
Single crystal silicon wafers are utilized for essentially all integrated circuits and many other semiconductor devices. To permit common processing equipment to be used in multiple device fabrication lines, it is essential for the wafer dimensions to be standardized.
In addition, as technology advances to smaller and smaller dimensions for the elements of high-density integrated circuits, it has become of interest to standardize additional properties of the wafers.
This Specification provides the essential dimensional and certain other common characteristics of silicon wafers, including polished wafers as well as substrates for epitaxial and certain other kinds of silicon wafers.
This Specification covers ordering information and certain requirements for high-purity (electronic grade), single crystal polished silicon wafers used in semiconductor device and integrated circuit manufacturing. Such wafers are usually sliced from cylindrical single-crystal ingots that have been ground to a uniform diameter prior to slicing. This Specification also covers ordering information and certain requirements for electronic grade silicon wafers intended for use as substrates (or starting wafers) for other kinds of wafers, including epitaxial, annealed, and SOI wafers.
Standardized dimensional requirements are provided for a large number of categories of standardized polished wafers as listed in the tables in § 6.
Values given for thickness, total thickness variation (TTV), bow, and warp apply only to wafers prior to application of back surface films, extrinsic gettering treatments, or other thermal treatments.
This Specification applies specifically to prime silicon wafers with at least one chem-mechanically polished surface. Ground, lapped, and unpolished wafers are not covered but this Specification may provide guidance in connection with their procurement.
This Specification also provides guides for the specification of 300 and 450 mm diameter prime silicon wafers for the 32, 22, and 16 nm technology generations. These are included in Related Information 1.
This Specification does not cover requirements for the following related types of silicon materials and wafers:
Polycrystalline silicon (see SEMI M16 or JEITA EM-3601A),
Epitaxial wafers (see SEMI M62),
Epitaxial wafers with buried layer (see SEMI M61),
Test wafers (see SEMI M8),
Premium wafers (see SEMI M24),
Reclaimed wafers (see SEMI M38),
Annealed wafers (see SEMI M57),
SOI wafers (see SEMI M41, SEMI M71, or JEITA EM-3603B), and
Solar-grade silicon wafers (see SEMI PV22).
Información adicional
| Autor | Semiconductor Equipment and Materials Institute (SEMI) |
|---|---|
| Publicado por | SEMI |
| Tipo de Documento | Norma |
