| Name | Unterstützung | Language | Verfügbarkeit | Datum der Ausstellung | Preis | ||
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PDF |
Englisch |
gültig |
01.01.2014 |
81,00 € |
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Details
This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5.
This document provides the test methodology details on:
CK and WCK Timings: tCK, tWCK, tCH/tCL, tWCKH/tWCKL, CK TJ/RJrms, CK and WCK Jitter
CK and WCK Input Operating Conditions: VIXCK, VIXWCK, VIDCK(ac), VIDWCK(ac), VIDCK(dc),
VIDWCK(dc), CKslew, and WCKslew
Data Input Timings: tDIVW, tDIPW
Note: The procedures described in this document are intended to provide information about the tests that will be used in JEDEC GDDR5 recommended measurement parameter. This testing is not a replacement for an exhaustive test validation plan.
Zusätzliche Information
| Autor | JEDEC Solid State Technology Association |
|---|---|
| Veröffentlicht von | JEDEC |
| Document type | Normen |
| Thema | /subgroups/37160 |
| Seitenzahl | 34 |
| Schlagwort | JEDEC JEP171 |
