| Nom | Support | Langue | Disponibilité | Date d'édition | Prix | ||
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PDF sécurisé |
Anglais |
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01/09/1996 |
204,00 € |
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Détails
This Standard was technically approved by the global Assembly & Packaging Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on August 18, 2017. Available at www.semiviews.org and www.semi.org in March 2018, originally published in 1980, previously published August 2011.
This Test Method describes the measurement method for the inductance of internal traces of semiconductor packages. This Test Method is applicable for the measurement of package inductance that is greater than 0.5 nH.
This Document describes the measurement of a pin grid array, one of the package types, as a sample. This Test Method is also applicable to other types of packages.
The inductance in this Document is limited to that of internal traces only and does not contain the portions contributed by the exposed areas such as pins and wires.
This Document uses SI units.
Informations supplémentaires
| Auteur | Semiconductor Equipment and Materials Institute (SEMI) |
|---|---|
| Edité par | SEMI |
| Type de document | Norme |
| Date de confirmation | 2018-03-01 |
