| Nom | Support | Langue | Disponibilité | Date d'édition | Prix | ||
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PDF sécurisé |
Anglais |
Active |
01/09/2014 |
204,00 € |
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Détails
This Guide is intended to address the needs of the 3D Stacked IC (3DS-IC) industry by providing the tools needed to procure wafer stacks to be used in a 3DS-IC process.
This Guide provides the tools to describe wafer stacks in a 3DS-IC process. A wafer stacking process takes two or more intermediate wafers and forms a stack, which can then be further processed as if it were a single wafer. After bonding the dimensions of the stack will no longer conform to standard thickness and/or diameter.
This Guide describes wafer stacks with nominal diameter of 300 mm, although the actual stack diameter may differ due to process and functional variation.
The diameters of the different wafers that comprise the stack may differ from each other.
Informations supplémentaires
| Auteur | Semiconductor Equipment and Materials Institute (SEMI) |
|---|---|
| Edité par | SEMI |
| Type de document | Norme |
| Date de confirmation | 2020-04-01 |
