| Nom | Support | Langue | Disponibilité | Date d'édition | Prix | ||
|---|---|---|---|---|---|---|---|
|
PDF |
Anglais |
Active |
19/05/2019 |
204,00 € |
|
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Détails
This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. The purpose is to provide a standard for the DDR4DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
Informations supplémentaires
| Auteur | JEDEC Solid State Technology Association |
|---|---|
| Edité par | JEDEC |
| Type de document | Norme |
| Thème | /subgroups/36440 |
| Mot-clé | JEDEC JESD82-32 |
