JEDEC JESD8-29:2016

JEDEC JESD8-29:2016

0.6 V Low Voltage Swing Terminated Logic (LVSTL06)

58,00 €

Détails

This standard defines power supply voltage range, dc interface, switching parameter and
overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital
circuits with 0.6V supply. The specifications in this standard represent a minimum set of
interface specifications for low voltage terminated circuits.

The purpose of this standard is to provide a standard of specification for uniformity, multiplicity
of sources, elimination of confusion, and ease of device specification and design by users.
Class 1 describes low VOH (Nominal VOH = VDDQ*0.5) level terminated electrical
characteristics. Class 2 describes high VOH (Nominal VOH = VDDQ*0.6) level terminated
electrical characteristics.

Informations supplémentaires

Auteur JEDEC Solid State Technology Association
Edité par JEDEC
Type de document Norme
Thème /subgroups/36080
Nombre de pages 14
Mot-clé JEDEC JESD8-29