| Nom | Support | Langue | Disponibilité | Date d'édition | Prix | ||
|---|---|---|---|---|---|---|---|
|
PDF |
Anglais |
Active |
01/11/2009 |
66,00 € |
|
||
Détails
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies.
Informations supplémentaires
| Auteur | JEDEC Solid State Technology Association |
|---|---|
| Edité par | JEDEC |
| Type de document | Norme |
| Thème | /subgroups/36080 |
| Nombre de pages | 23 |
| Mot-clé | JEDEC JEP158 |
