| Nom | Support | Langue | Disponibilité | Date d'édition | Prix | ||
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PDF |
Anglais |
Active |
12/10/2022 |
156,00 € |
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Papier |
Anglais |
Active |
12/10/2022 |
194,00 € |
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Détails
Revision Standard - Active.
A mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrators.
IEEE Std 1500 is a standard design-for-testability method for integrated circuits (ICs) containing embedded nonmergeable cores. This method is independent of the underlying functionality of the IC or its individual embedded cores. The method supports the necessary requirements for the test of such ICs, while allowing for ease of interoperability of cores that might have originated from different sources. This method is usable for all classes of digital cores, including hierarchical cores.
The aim of IEEE Std 1500 is to provide a consistent scalable solution to the test reuse challenges specific to the reuse of nonmergeable cores, while preserving the IP aspects that are often associated with these cores. This objective is achieved through provision of a core-centric methodology that enables successful integration of cores into SoCs.
Informations supplémentaires
| Auteur | Institute of Electrical and Electronics Engineers (IEEE) |
|---|---|
| Comité | Test Technology |
| Edité par | IEEE |
| Type de document | Norme |
| Edition révision n° | 0 |
| EAN ISBN | 978-1-5044-8866-2 |
| ICS | 31.200 : Circuits intégrés. micro-électronique
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| Nombre de pages | 168 |
| Remplace | IEEE 1500:2005 (R2011) |
| Mot-clé | IEEE 1500-2022 |
| Bon de commande |
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