IEC 62530:2021

IEC 62530:2021

IEC 62530:2021 SystemVerilog - Unified Hardware Design, Specification, and Verification Language

489,00 €

Détails

IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions, testbench, coverage, assertion, object-oriented, and constrained random constructs, and also provides application programming interfaces (APIs) to foreign programming languages.
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.

Informations supplémentaires

Auteur International Electrotechnical Commission (IEC)
Comité TC 91
Edité par IEC
Type de document Norme
Edition révision n° 3
ICS 25.040.01 : Systèmes d'automatisation industrielle en général
35.060 : Langages utilisés dans les technologies de l'information
Nombre de pages 1315
Remplace IEC 62530:2011
Historique IEC 62530:2011
Mot-clé IEC62530,IEC 62530:2021,IEC 62530,TC 91