JEDEC
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JEDEC JESD8-12A.01:2007
1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
9/1/2007 - PDF - English - JEDEC
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JEDEC JESD84-A42:2007
EMBEDDED MULTIMEDIACARD (e*MMC) PRODUCT STANDARD, HIGH CAPACITY
7/1/2007 - PDF - English - JEDEC
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JEDEC JESD84-B42:2007
MULTIMEDIACARD (MMC) ELECTRICAL STANDARD, HIGH CAPACITY (MMCA, 4.2)
7/1/2007 - PDF - English - JEDEC
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JEDEC JESD84-A41:2007
EMBEDDED MULTIMEDIACARD (e*MMC) PRODUCT STANDARD, STANDARD CAPACITY
7/1/2007 - PDF - English - JEDEC
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JEDEC JESD84-B41:2007
MULTIMEDIACARD (MMC) ELECTRICAL STANDARD, STANDARD CAPACITY (MMCA, 4.1)
6/1/2007 - PDF - English - JEDEC
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JEDEC JESD 82-26:2007
DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS
5/1/2007 - PDF - English - JEDEC
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JEDEC JEP152:2007
DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD
5/1/2007 - PDF - English - JEDEC
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JEDEC JESD82-19A:2007
DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
5/1/2007 - PDF - English - JEDEC
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JEDEC JESD 82-23:2007
DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
5/1/2007 - PDF - English - JEDEC
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JEDEC JESD82-10A:2007
DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
5/1/2007 - PDF - English - JEDEC
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JEDEC JESD82-9B:2007
DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS
5/1/2007 - PDF - English - JEDEC
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JEDEC JESD8-3A:2007
ADDENDUM No. 3A to JESD8 - GUNNING TRANSCEIVER LOGIC (GTL) LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
5/1/2007 - PDF - English - JEDEC
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JEDEC JESD82-16A:2007
DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS
5/1/2007 - PDF - English - JEDEC
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JEDEC JESD 82-12A:2007
DEFINITION OF THE SSTU32S869 & SSTU32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
4/1/2007 - PDF - English - JEDEC
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JEDEC JESD207:2007
RADIO FRONT END - BASEBAND DIGITAL PARALLEL (RBDP) INTERFACE
3/1/2007 - PDF - English - JEDEC
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JEDEC JESD205:2007
FBDIMM STANDARD: DDR2 SDRAM FULLY BUFFERED DIMM (FBDIMM) DESIGN SPECIFICATION
3/1/2007 - PDF - English - JEDEC
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JEDEC JESD74A:2007 (R2019)
EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTS
2/1/2007 - PDF - English - JEDEC
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JEDEC JESD82-21:2007
STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS
1/1/2007 - PDF - English - JEDEC
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JEDEC JESD51-2A:2007
INTEGRATED CIRCUITS THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - NATURAL CONVECTION (STILL AIR)
1/1/2007 - PDF - English - JEDEC
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JEDEC JESD82-18A:2007
STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERSFOR REGISTERED DDR2 DIMM APPLICATIONS
1/1/2007 - PDF - English - JEDEC
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JEDEC JESD96A-1:2007
Addendum 1 to JESD96A - INTEROPERABILITY AND COMPLIANCE TECHNICAL REQUIREMENTS FOR JEDEC STANDARD JESD96A - RECOMMENDED PRACTICE FOR USE WITH IEEE 802.11N
1/1/2007 - PDF - English - JEDEC
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€58.00
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JEDEC JESD82-14A:2006
DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
10/1/2006 - PDF - English - JEDEC
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JEDEC JEP121A:2006
REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION
10/1/2006 - PDF - English - JEDEC
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JEDEC JESD89A:2006
MEASUREMENT AND REPORTING OF ALPHA PARTICLE AND TERRESTRIAL COSMIC RAY INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES
10/1/2006 - PDF - English - JEDEC
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JEDEC JEP179:2006
DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION
6/1/2006 - PDF - English - JEDEC
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JEDEC JESD8-7A:2006
ADDENDUM No. 7 to JESD8 - 1.8 V + -0.15 V (NORMAL RANGE), AND 1.2 V - 1.95 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT
6/1/2006 - PDF - English - JEDEC
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JEDEC JESD202:2006
METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESS
3/1/2006 - PDF - English - JEDEC
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JEDEC JP 002:2006
CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINE
3/1/2006 - PDF - English - JEDEC
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JEDEC JESD75-6:2006
PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONS
3/1/2006 - PDF - English - JEDEC
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€113.00
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JEDEC JESD203:2005
STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES
11/1/2005 - PDF - English - JEDEC
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JEDEC JESD82-15:2005
STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS
11/1/2005 - PDF - English - JEDEC
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JEDEC JS 9704:2005
IPC/JEDEC-9704: Printed Wiring Board (PWB) Strain Gage Test Guideline
6/1/2005 - PDF - English - JEDEC
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JEDEC JESD90:2004
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES
11/1/2004 - PDF - English - JEDEC
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€63.00
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JEDEC JESD8-17:2004
DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS
11/1/2004 - PDF - English - JEDEC
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€72.00
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JEDEC JESD82-11:2004
DEFINITION OF 'CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS
9/1/2004 - PDF - English - JEDEC
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JEDEC JESD60A:2004
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
9/1/2004 - PDF - English - JEDEC
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JEDEC JESD75-5:2004
SON/QFN PACKAGE PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS
7/1/2004 - PDF - English - JEDEC
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JEDEC JS 9702:2004
IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)
6/1/2004 - PDF - English - JEDEC
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JEDEC JESD24-12:2004
THERMAL IMPEDANCE MEASUREMENT FOR INSULATED GATE BIPOLAR TRANSISTORS - (Delta VCE(on) Method)
6/1/2004 - PDF - English - JEDEC
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JEDEC JEP84A:2004
RECOMMENDED PRACTICE FOR MEASUREMENT OF TRANSISTOR LEAD TEMPERATURE
6/1/2004 - PDF - English - JEDEC
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JEDEC JESD82-1A:2004
DEFINITION OF CVF857 PLL CLOCK DRIVER FOR REGISTERED PC1600, PC2100, PC2700, AND PC3200 DIMM APPLICATIONS
5/1/2004 - PDF - English - JEDEC
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€57.00
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JEDEC JESD75-4:2004
BALL GRID ARRAY PINOUT FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS
3/1/2004 - PDF - English - JEDEC
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JEDEC JESD82-8.01:2004
STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS
2/1/2004 - PDF - English - JEDEC
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JEDEC JESD33-B:2004
STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE
2/1/2004 - PDF - English - JEDEC
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JEDEC JEP147:2003
PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)
10/1/2003 - PDF - English - JEDEC
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JEDEC JESD65B:2003
DEFINITION OF SKEW SPECIFICATIONS FOR STANDARD LOGIC DEVICES
9/1/2003 - PDF - English - JEDEC
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€66.00
-
€64.00
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JEDEC JESD92:2003
PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS
8/1/2003 - PDF - English - JEDEC
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€79.00
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€51.00
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JEDEC JESD82-4B:2003
STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS
5/1/2003 - PDF - English - JEDEC
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€64.00
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JEDEC JEP104C.01:2003
REFERENCE GUIDE TO LETTER SYMBOLS FOR SEMICONDUCTOR DEVICES
5/1/2003 - PDF - English - JEDEC
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JEDEC JEP145:2003
GUIDELINE FOR ASSESSING THE CURRENT-CARRYING CAPABILITY OF THE LEADS IN A POWER PACKAGE SYSTEM
2/1/2003 - PDF - English - JEDEC
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JEDEC JESD100B.01:2002
TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROCOMPUTERS, MICROPROCESSORS, AND MEMORY INTEGRATED CIRCUITS
12/1/2002 - PDF - English - JEDEC
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JEDEC JESD82-5:2002
STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION
7/1/2002 - PDF - English - JEDEC
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JEDEC JEP140:2002 (R2015) (R2006)
BEADED THERMOCOUPLE TEMPERATURE MEASUREMENT OF SEMICONDUCTOR PACKAGES
6/1/2002 - PDF - English - JEDEC
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JEDEC JESD 8-9B:2002
ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002
5/1/2002 - PDF - English - JEDEC
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JEDEC JESD28-A:2001
A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS
12/1/2001 - PDF - English - JEDEC
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JEDEC JESD73-4:2001
STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH
11/1/2001 - PDF - English - JEDEC
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JEDEC JESD73-3:2001
STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCH
11/1/2001 - PDF - English - JEDEC
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JEDEC JESD75-1:2001
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE
10/1/2001 - PDF - English - JEDEC
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JEDEC JESD 24-6(R2002):2001
ADDENDUM No. 6 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR INSULATED GATE BIPOLAR TRANSISTORS
10/1/2001 - PDF - English - JEDEC
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€57.00
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€58.00
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€51.00
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JEDEC JESD73-2:2001
STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS
8/1/2001 - PDF - English - JEDEC
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JEDEC JESD73-1:2001
STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES
8/1/2001 - PDF - English - JEDEC
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JEDEC JESD75-2:2001
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16-BIT LOGIC FUNCTIONS
7/1/2001 - PDF - English - JEDEC
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€77.00
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JEDEC JESD82-2:2001
STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS
7/1/2001 - PDF - English - JEDEC
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JEDEC JESD87:2001
STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALS
7/1/2001 - PDF - English - JEDEC
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JEDEC JESD75-3:2001
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS
7/1/2001 - PDF - English - JEDEC
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JEDEC JESD76-1:2001
STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION)
6/1/2001 - PDF - English - JEDEC
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JEDEC JESD76-2:2001
STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION)
6/1/2001 - PDF - English - JEDEC
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JEDEC JESD51-11:2001
TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADED PACKAGE THERMAL MEASUREMENT
6/1/2001 - PDF - English - JEDEC
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JEDEC JEP139:2000
GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING
12/1/2000 - PDF - English - JEDEC
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JEDEC JESD64-A:2000
STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS
10/1/2000 - PDF - English - JEDEC
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JEDEC JESD82:2000
DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS
7/1/2000 - PDF - English - JEDEC
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JEDEC JESD51-10:2000
TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADED PACKAGE THERMAL MEASUREMENTS
7/1/2000 - PDF - English - JEDEC
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JEDEC JESD51-9:2000
TEST BOARDS FOR AREA ARRAY SURFACE MOUNT PACKAGE THERMAL MEASUREMENTS
7/1/2000 - PDF - English - JEDEC
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€151.00
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€51.00
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JEDEC JESD286-B(R2005):2000
STANDARD FOR MEASURING FORWARD SWITCHING CHARACTERISTICS OF SEMICONDUCTOR DIODES
2/1/2000 - PDF - English - JEDEC
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€51.00
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JEDEC JESD75:1999
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 32-BIT LOGIC FUNCTIONS
11/1/1999 - PDF - English - JEDEC
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JEDEC JESD66(R2006):1999
TRANSIENT VOLTAGE SUPPRESSOR STANDARD FOR THYRISTOR SURGE PROTECTIVE DEVICE
11/1/1999 - PDF - English - JEDEC
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JEDEC JESD51-8:1999
INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - JUNCTION-TO-BOARD
10/1/1999 - PDF - English - JEDEC
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JEDEC JEP138:1999
USER GUIDELINES FOR IR THERMAL IMAGING DETERMINATION OF DIE TEMPERATURE
9/1/1999 - PDF - English - JEDEC
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€93.00
-
€63.00
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JEDEC JESD73:1999
DESCRIPTION OF 5 V BUS SWITCH WITH TTL-COMPATIBLE CONTROL INPUTS
6/1/1999 - PDF - English - JEDEC
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JEDEC JESD70:1999
2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTS
6/1/1999 - PDF - English - JEDEC
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JEDEC JESD51-6:1999
INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONVECTION (MOVING AIR)
3/1/1999 - PDF - English - JEDEC
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JEDEC JESD51-5:1999
EXTENSION OF THERMAL TEST BOARD STANDARDS FOR PACKAGES WITH DIRECT THERMAL ATTACHMENT MECHANISMS
2/1/1999 - PDF - English - JEDEC
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JEDEC JESD51-7:1999
HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES
2/1/1999 - PDF - English - JEDEC
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JEDEC JESD67:1999
I/O DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATION VOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLD
2/1/1999 - PDF - English - JEDEC
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JEDEC JEP134:1998
GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS
9/1/1998 - PDF - English - JEDEC
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JEDEC JESD63:1998
STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE
2/1/1998 - PDF - English - JEDEC
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€60.00
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JEDEC JESD57:1996
TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION
12/1/1996 - PDF - English - JEDEC
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JEDEC JEP128:1996
GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING
11/1/1996 - PDF - English - JEDEC
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JEDEC JESD 24-11(R2002):1996
ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD
8/1/1996 - PDF - English - JEDEC
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JEDEC JESD51-3:1996
LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES
8/1/1996 - PDF - English - JEDEC
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JEDEC JESD8-8:1996
ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
8/1/1996 - PDF - English - JEDEC
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JEDEC JEP103A(R2003):1996
SUGGESTED PRODUCT-DOCUMENTATION, CLASSIFICATIONS, AND DISCLAIMERS
7/1/1996 - PDF - English - JEDEC
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JEDEC EIA 318-B:1996
MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODES
7/1/1996 - PDF - English - JEDEC
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JEDEC JESD 36:1996
STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES
6/1/1996 - PDF - English - JEDEC
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€63.00
-
JEDEC JESD55:1996
STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES
5/1/1996 - PDF - English - JEDEC
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JEDEC JEP126:1996
GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FROM COMPUTATIONAL ANALYSIS
5/1/1996 - PDF - English - JEDEC
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JEDEC JESD 35-2:1996
ADDENDUM No. 2 to JESD35 - TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS
2/1/1996 - PDF - English - JEDEC
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JEDEC JESD54:1996
STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES
2/1/1996 - PDF - English - JEDEC
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JEDEC JESD51:1995
METHODOLOGY FOR THE THERMAL MEASUREMENT OF COMPONENT PACKAGES (SINGLE SEMICONDUCTOR DEVICE)
12/1/1995 - PDF - English - JEDEC
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€58.00
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JEDEC JESD51-1:1995
INTEGRATED CIRCUIT THERMAL MEASUREMENT METHOD - ELECTRICAL TEST METHOD (SINGLE SEMICONDUCTOR DEVICE)
12/1/1995 - PDF - English - JEDEC
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JEDEC JESD52:1995
STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES
11/1/1995 - PDF - English - JEDEC
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JEDEC JEP123:1995
GUIDELINE FOR MEASUREMENT OF ELECTRONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL PARAMETERS
10/1/1995 - PDF - English - JEDEC
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JEDEC JESD 35-1:1995
ADDENDUM No. 1 to JESD35 - GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS
9/1/1995 - PDF - English - JEDEC
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JEDEC JESD8-6:1995
ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
8/1/1995 - PDF - English - JEDEC
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JEDEC JESD 24-10(R2002):1994
ADDENDUM No. 10 to JESD24 - TEST METHOD FOR MEASUREMENT OF REVERSE RECOVERY TIME trr FOR POWER MOSFET DRAIN-SOURCE DIODES
8/1/1994 - PDF - English - JEDEC
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JEDEC JESD3-C:1994
STANDARD DATA TRANSFER FORMAT BETWEEN DATA PREPARATION SYSTEM AND PROGRAMMABLE LOGIC DEVICE PROGRAMMER
6/1/1994 - PDF - English - JEDEC
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JEDEC JESD8-4:1993
ADDENDUM No. 4 to JESD8 - CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
11/1/1993 - PDF - English - JEDEC
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JEDEC JESD 27:1993
CERAMIC PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES
8/1/1993 - PDF - English - JEDEC
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JEDEC JESD 12-1B:1993
ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS
8/1/1993 - PDF - English - JEDEC
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JEDEC JESD8-2:1993
ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITS
3/1/1993 - PDF - English - JEDEC
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JEDEC JESD18-A:1993
STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC
1/1/1993 - PDF - English - JEDEC
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€50.00
-
JEDEC JESD 37:1992
STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD
10/1/1992 - PDF - English - JEDEC
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JEDEC JESD 24-9(R2002):1992
ADDENDUM No. 9 to JESD24 - SHORT CIRCUIT WITHSTAND TIME TEST METHOD
8/1/1992 - PDF - English - JEDEC
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JEDEC JESD 24-8(R2002):1992
ADDENDUM No. 8 to JESD24 - METHOD FOR REPETITIVE INDUCTIVE LOAD AVALANCHE SWITCHING
8/1/1992 - PDF - English - JEDEC
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JEDEC JES 2:1992
TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION
7/1/1992 - PDF - English - JEDEC
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€151.00
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JEDEC JESD 12-6:1991
ADDENDUM No. 6 to JESD12 - INTERFACE STANDARD FOR SEMICUSTOM INTEGRATED CIRCUITS
3/1/1991 - PDF - English - JEDEC
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€57.00
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JEDEC JESD 24-4(R2002):1990
ADDENDUM No. 4 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR BIPOLAR TRANSISTORS (DELTA BASE-EMITTER VOLTAGE METHOD)
11/1/1990 - PDF - English - JEDEC
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JEDEC JESD 24-3:1990
ADDENDUM No. 3 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR VERTICAL POWER MOSFETS (DELTA SOURCE-DRAIN VOLTAGE METHOD)
11/1/1990 - PDF - English - JEDEC
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JEDEC JESD20:1990
STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES
9/1/1990 - PDF - English - JEDEC
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JEDEC JESD 24-5(R2002):1990
ADDENDUM No. 5 to JESD24 - SINGLE PULSE UNCLAMPED INDUCTIVE SWITCHING (UIS) AVALANCHE TEST METHOD
8/1/1990 - PDF - English - JEDEC
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JEDEC JESD 24-1(R2002):1989
ADDENDUM No. 1 to JESD24 - METHOD FOR MEASUREMENT OF POWER DEVICE TURN-OFF SWITCHING LOSS
10/1/1989 - PDF - English - JEDEC
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€57.00
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JEDEC JESD 12-5:1988
ADDENDUM No. 5 to JESD12 - DESIGN FOR TESTABILITY GUIDELINES
8/1/1988 - PDF - English - JEDEC
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JEDEC JEP110:1988
GUIDELINES FOR THE MEASUREMENT OF THERMAL RESISTANCE OF GaAs FETS
7/1/1988 - PDF - English - JEDEC
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JEDEC JESD 12-4:1987
ADDENDUM No. 4 to JESD12 - METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INTEGRATED CIRCUITS
4/1/1987 - PDF - English - JEDEC
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JEDEC JESD 321-C(R2009):1987
NUMBERING OF LIKE-NAMED TERMINAL FUNCTIONS IN SEMICONDUCTOR DEVICES AND DESIGNATION OF UNITS IN MULTIPLE-UNIT SEMICONDUCTOR DEVICES
2/1/1987 - PDF - English - JEDEC
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€63.00
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JEDEC JEP64(R2002):1986
SOLID STATE PRODUCTS REGISTRATION LIST(ORDER FROM TYPE ADMINISTRATION OFFICE)
9/1/1986 - PDF - English - JEDEC
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JEDEC JESD7-A:1986
STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES
8/1/1986 - PDF - English - JEDEC
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JEDEC JESD531(R2002):1986
THERMAL RESISTANCE TEST METHOD FOR SIGNAL AND REGULATOR DIODES (FORWARD VOLTAGE, SWITCHING METHOD)
7/1/1986 - PDF - English - JEDEC
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JEDEC JESD 12-3:1986
ADDENDUM No. 3 to JESD12 - CMOS GATE ARRAY MACROCELL STANDARD
6/1/1986 - PDF - English - JEDEC
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€55.00
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JEDEC JESD 12-2:1986
ADDENDUM No. 2 to JESD12 - STANDARD FOR CELL-BASED INTEGRATED CIRCUIT BENCHMARK SET
2/1/1986 - PDF - English - JEDEC
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€97.00
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JEDEC JESD12:1985
SEMICUSTOM INTEGRATED CIRCUITS (FORMERLY PUBLISHED AS STANDARD FOR GATE ARRAY BENCHMARK SET)
6/1/1985 - PDF - English - JEDEC
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JEDEC JESD11:1984
CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS
12/1/1984 - PDF - English - JEDEC
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JEDEC JESD 482-A(R2002):1984
LIST OF PREFERRED VALUES FOR USE ON VARIOUS TYPES OF SMALL SIGNAL AND REGULATOR DIODES
8/1/1984 - PDF - English - JEDEC
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JEDEC JESD4(R2002):1983
DEFINITION OF EXTERNAL CLEARANCE AND CREEPAGE DISTANCES OF DISCRETE SEMICONDUCTOR PACKAGES FOR THYRISTORS AND RECTIFIER DIODES
11/1/1983 - PDF - English - JEDEC
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€57.00
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JEDEC JESD 24-7(R2002):1982
ADDENDUM No. 7 to JESD24 - COMMUTATING DIODE SAFE OPERATING AREA TEST PROCEDURE FOR MEASURING dv/dt DURING REVERSE RECOVERY OF POWER TRANSISTORS
8/1/1982 - PDF - English - JEDEC
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JEDEC JESD 23:1982
TEST METHODS AND CHARACTER DESIGNATION FOR LIQUID CRYSTAL DEVICES:
5/1/1982 - PDF - English - JEDEC
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€57.00
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€58.00
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JEDEC JESD 5(R2002):1982
MEASUREMENT OF TEMPERATURE COEFFICIENT OF VOLTAGE REGULATOR DIODES
2/1/1982 - PDF - English - JEDEC
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JEDEC JESD311-A(R2009):1981
MEASUREMENT OF TRANSISTOR NOISE FIGURE AT MF, HF, AND VHF
11/1/1981 - PDF - English - JEDEC
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€64.00
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JEDEC JESD419-A(R2001):1980
STANDARD LIST OF VALUES TO BE USED IN SEMICONDUCTOR DEVICE SPECIFICATIONS AND REGISTRATION FORMAT
10/1/1980 - PDF - English - JEDEC
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€113.00
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JEDEC JESD13-B:1980
STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS DEVICES
5/1/1980 - PDF - English - JEDEC
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€51.00
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JEDEC JESD 435(R2009):1976
STANDARD FOR THE MEASUREMENT OF SMALL-SIGNAL TRANSISTOR SCATTERING PARAMETERS
4/1/1976 - PDF - English - JEDEC
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€204.00
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JEDEC JESD313-B(R2001):1975
THERMAL RESISTANCE MEASUREMENTS OF CONDUCTION COOLED POWER TRANSISTORS
10/1/1975 - PDF - English - JEDEC
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JEDEC JEP69-B(R1999):1973
PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS
11/1/1973 - PDF - English - JEDEC
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€63.00
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€55.00
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JEDEC JESD25(R2002):1972
MEASUREMENT OF SMALL-SIGNAL TRANSISTOR SCATTERING PARAMETERS
11/1/1972 - PDF - English - JEDEC
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€58.00
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€244.00
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JEDEC JESD 372(R2009):1970
THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR ADMITTANCE PARAMETERS
5/1/1970 - PDF - English - JEDEC
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JEDEC JESD 371(R2009):1970
THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR SHORT-CIRCUIT FORWARD CURRENT TRANSFER RATIO
2/1/1970 - PDF - English - JEDEC
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JEDEC JEB 5-A:1970 (R1984)
METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITS
- PDF - English - JEDEC
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JEDEC JEB 15:1969
TERMINOLOGY AND METHODS OF MEASUREMENT FOR BISTABLE SEMICONDUCTOR MICROCIRCUITS
11/1/1969 - PDF - English - JEDEC
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JEDEC EIA 365(R1984):1969
PERFORMANCE TEST PROCEDURE FOR SOLAR CELLS AND CALIBRATION PROCEDURE FOR SOLAR CELL STANDARDS FOR SPACE VEHICLE SERVICE
11/1/1969 - PDF - English - JEDEC
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JEDEC JEP78:1969
RELATIVE SPECTRAL RESPONSE CURVES FOR SEMICONDUCTOR INFRARED DETECTORS
10/1/1969 - PDF - English - JEDEC
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€72.00
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JEDEC JESD 353(R2009):1968
THE MEASUREMENT OF TRANSISTOR NOISE FIGURE AT FREQUENCIES UP TO 20 kHz BY SINUSOIDAL SIGNAL-GENERATOR METHOD
4/1/1968 - PDF - English - JEDEC
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JEDEC JESD 354(R2009):1968
THE MEASUREMENT OF TRANSISTOR EQUIVALENT NOISE VOLTAGE AND EQUIVALENT NOISE CURRENT AT FREQUENCIES OF UP TO 20 kHz
4/1/1968 - PDF - English - JEDEC
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JEDEC JEP65(R1999):1967
TEST PROCEDURES FOR VERIFICATION OF MAXIMUM RATINGS OF POWER TRANSISTORS
12/1/1967 - PDF - English - JEDEC
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€58.00
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€63.00
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JEDEC EIA 323(R2002):1966
AIR-CONVECTION-COOLED, LIFE TEST ENVIRONMENT FOR LEAD-MOUNTED SEMICONDUCTOR DEVICES
3/1/1966 - PDF - English - JEDEC
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€51.00
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JEDEC JESD306:1965 (R2009)
MEASUREMENT OF SMALL SIGNAL HF, VHF, AND UHF POWER GAIN OF TRANSISTORS
5/1/1965 - PDF - English - JEDEC
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JEDEC JESD302(R2009):1965
RANGES AND CONDITIONS FOR SPECIFYING BETA FOR LOW POWER, AUDIO FREQUENCY TRANSISTORS FOR ENTERTAINMENT SERVICE
1/1/1965 - PDF - English - JEDEC
Learn More€50.00