| Name | Support | Language | Availability | Edition date | Price | ||
|---|---|---|---|---|---|---|---|
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PDF |
English |
Active |
2/1/2014 |
€93.00 |
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Details
This document provides a guideline for the minimum set of measurements to qualify a new semiconductor wafer process. It is written with particular reference to a generic silicon based CMOS logic technology. While it may be applicable to other technologies (e.g., analog CMOS, bipolar, BICMOS, GaAs, etc.), some sections apply specifically to CMOS. No effort was made in the present document to cover all the qualification requirements for specific other technologies, e.g., Cu/Low K interconnects or ultra thin gate oxide. This publication, is co-sponsored by JEDEC JC-14.2 and the FSA (Fabless Semiconductor Association). It originated at the FSA as a technology specific document, and has evolved into a generic set of qualification requirements.
Additional Info
| Author | JEDEC Solid State Technology Association |
|---|---|
| Published by | JEDEC |
| Document type | Standard |
| Theme | /subgroups/36080 |
| Number of pages | 48 |
| Replace | JEDEC JP001.01 |
| Keyword | JEDEC JP001A |
