| Name | Support | Language | Availability | Edition date | Price | ||
|---|---|---|---|---|---|---|---|
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PDF |
English |
Active |
7/1/2021 |
€58.24 |
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Details
This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources.
Additional Info
| Author | JEDEC Solid State Technology Association |
|---|---|
| Published by | JEDEC |
| Document type | Standard |
| Theme | /subgroups/36080 |
| ICS | 31.080.01 : Semiconductor devices in general
|
| Number of pages | 16 |
| Replace | JEDEC JESD89-1A:2007 (R2012) |
| Keyword | JEDEC JESD89-1A |
