| Name | Support | Language | Availability | Edition date | Price | ||
|---|---|---|---|---|---|---|---|
|
PDF sécurisé |
English |
Active |
1/1/2020 |
€54.33 |
|
||
Details
The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes and simultaneously the operating biases are periodically applied and removed. It is intended to simulate worst case conditions encountered in application environments. The power and temperature cycling test is considered destructive and is only intended for device qualification. This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures.
Additional Info
| Author | JEDEC Solid State Technology Association (JEDEC) |
|---|---|
| Published by | JEDEC |
| Document type | Standard |
| ICS | 17.200.20 : Temperature-measuring instruments
|
| Number of pages | 12 |
| Replace | EIA JESD 22-A105C:2004 (R2011) |
