JEDEC JEP158:2009

JEDEC JEP158:2009

3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions

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Details

To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies.

Additional Info

Author JEDEC Solid State Technology Association
Published by JEDEC
Document type Standard
Theme /subgroups/36080
Number of pages 23
Keyword JEDEC JEP158