| Name | Support | Language | Availability | Edition date | Price | ||
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PDF |
English, French |
Active |
8/7/2013 |
€173.00 |
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Details
IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report:
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.
Additional Info
| Author | International Electrotechnical Commission (IEC) |
|---|---|
| Committee | TC 91 |
| Published by | IEC |
| Document type | Standard |
| Edition | 1.0 |
| ICS | 25.040.01 : Industrial automation systems in general
35.240.50 : IT applications in industry |
| Number of pages | 42 |
| Keyword | IEC62856,IEC TR 62856:2013,IEC/TR 62856,TC 91 |
